#include <stdlib.h>
#include <iostream>
#include <verilated.h>
#include <verilated_vcd_c.h>
#include "VRegisterFile__Syms.h"
using namespace std;


#define MAX_SIM_TIME 64
vluint64_t sim_time = 0;
uint64_t rand_uint64_slow(void) {
  uint64_t r = 0;
  for (int i=0; i<64; i++) {
    r = r*2 + rand()%2;
  }
  return r;
}

int reg_write(VRegisterFile *dut, uint8_t reg, u_int64_t data, uint8_t wen);

int main(int argc, char** argv, char** env) {
    VRegisterFile *dut = new VRegisterFile;
    uint64_t a = 1;
    uint8_t reg = 0;
    Verilated::traceEverOn(true);
    VerilatedVcdC *m_trace = new VerilatedVcdC;
    dut->trace(m_trace, 5);
    m_trace->open("wave.vcd");
    while (sim_time < MAX_SIM_TIME) {
        dut->clk ^= 1;
        if(dut->clk){
            a=rand_uint64_slow();
            reg_write(dut, reg, a, 1);
        }    
        if(sim_time>= 30 && sim_time< 40){
            dut->rst=1;
        }
        else
            dut->rst=0;
        dut->eval();
        m_trace->dump(sim_time);
        if(dut->clk)
        {
            cout << "num="<<a<<" reg="<<(int)reg<<" busA="<<dut->rdataA<<" busB="<<dut->rdataB<<endl;
            reg = (reg+1)%32;
        }
        sim_time++;

    }
    m_trace->close();
    delete dut;
    exit(EXIT_SUCCESS);
}

int reg_write(VRegisterFile *dut, uint8_t reg, u_int64_t data, uint8_t wen){
    dut->waddr = reg;
    dut->wen = wen;
    dut->wdata = data;
    dut->raddrA = reg;
    dut->raddrB = reg;
    return 0;
}